TY - GEN
T1 - PID-controlled PLL for fast frequency-hopped systems
AU - Uyanik, Hayri Ugur
AU - Tarim, Nil
PY - 2007
Y1 - 2007
N2 - In this work, a novel aided-acquisition technique based on proportional-integral-derivative (PID) control of a phase-locked loop (PLL) is presented. This is achieved by inserting a control block into the PLL during acquisition where originally the output frequency/phase is controlled by a PI controller. This significantly reduces the settling time of the PLL which is important for certain applications such as WLANs where fast frequency-hopped spread-spectrum methods are used. Simulations show that the proposed structure reduces the settling time by 75%.
AB - In this work, a novel aided-acquisition technique based on proportional-integral-derivative (PID) control of a phase-locked loop (PLL) is presented. This is achieved by inserting a control block into the PLL during acquisition where originally the output frequency/phase is controlled by a PI controller. This significantly reduces the settling time of the PLL which is important for certain applications such as WLANs where fast frequency-hopped spread-spectrum methods are used. Simulations show that the proposed structure reduces the settling time by 75%.
UR - http://www.scopus.com/inward/record.url?scp=48349094502&partnerID=8YFLogxK
U2 - 10.1109/DCAS.2007.4433198
DO - 10.1109/DCAS.2007.4433198
M3 - Conference contribution
AN - SCOPUS:48349094502
SN - 9781424416806
T3 - 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07
SP - 117
EP - 119
BT - 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC)
T2 - 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07
Y2 - 15 November 2007 through 16 November 2007
ER -