Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

Sajjad Parvin*, Mustafa Altun

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


Reversible logic has 100% fault observability meaning that a fault in any circuit node propagates to the output stage. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible logic to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED) capability. For this purpose, we propose a new fault preservative reversible gate library called Even Target - Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPMCT, we ensure that the evenness/oddness of applied 1's at input, is preserved at all levels of a circuit including output level unless there is a faulty node. A single fault always destroys the parity of input at the output. Our design strategy has two steps for a given function: 1) implement the function with our proposed reversible ET-MPMCT gate library; and 2) apply reversible-to-CMOS gate conversion. For the first step, we propose two approaches. For our first approach in step 1, we first need to have a reversible form of the given function if it is irreversible. Then, synthesize the reversible function using Mixed Polarity Multiple Control Toffoli (MPMCT) gate library by conventional reversible logic synthesis techniques. Finally, the synthesized circuit is converted to ET-MPMCT constructed circuit which is fault preservative. Our second approach, is an ESOP - Exclusive Sum of Products - based synthesis approach modified for our proposed fault preservative ET-MPMCT gate library. It does work with both irreversible and reversible functions. We synthesize our circuits with both approaches in step 1 and choose the circuit with lower number of reversible gates to be fed to step 2 of our design strategy. In second step of our design strategy, we convert our fault preservative reversible circuits into their CMOS counterparts. The performance of our designs is compared with other CED schemes in the literature in terms of area, power consumption, delay and detection rate. Simulations are done with Cadence Genus tool using TSMC 40nm technology. Clearly, results are in favor of our proposed techniques.

Original languageEnglish
Article number8890724
Pages (from-to)163939-163947
Number of pages9
JournalIEEE Access
Publication statusPublished - 2019

Bibliographical note

Publisher Copyright:
© 2013 IEEE.


This work was supported in part by the TUBITAK-1002 under Project 215E268, and in part by the Istanbul Technical University BAP under Project #41956.

FundersFunder number
Istanbul Technical University BAP
Istanbul Teknik Üniversitesi41956


    • concurrent error detection
    • fault preservation
    • fault tolerant CMOS
    • latent faults
    • QCA
    • quantum computing
    • Reversible logic


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