Abstract
The size of counterfeiting activities is increasing day by day. These activities are encountered especially in electronics market. In this paper, a countermeasure against counterfeiting on intellectual properties (IP) on Field-Programmable Gate Arrays (FPGA) is proposed. FPGA vendors provide bitstream ciphering as an IP security solution such as battery-backed or non-volatile FPGAs. However, these solutions are secure as long as they can keep decryption key away from third parties. Key storage and key transfer over unsecure channels expose risks for these solutions. In this work, physical unclonable functions (PUFs) have been used for key generation. Generating a key from a circuit in the device solves key transfer problem. Proposed system goes through different phases when it operates. Therefore, partial reconfiguration feature of FPGAs is essential for feasibility of proposed system.
Original language | English |
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Title of host publication | Proceedings - 2017 1st New Generation of CAS, NGCAS 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 65-68 |
Number of pages | 4 |
ISBN (Electronic) | 9781509064472 |
DOIs | |
Publication status | Published - 26 Sept 2017 |
Event | 1st New Generation of CAS, NGCAS 2017 - Genova, Italy Duration: 6 Sept 2017 → 9 Sept 2017 |
Publication series
Name | Proceedings - 2017 1st New Generation of CAS, NGCAS 2017 |
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Conference
Conference | 1st New Generation of CAS, NGCAS 2017 |
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Country/Territory | Italy |
City | Genova |
Period | 6/09/17 → 9/09/17 |
Bibliographical note
Publisher Copyright:© 2017 IEEE.
Keywords
- FPGAs
- Hardware Security
- IP Protection
- Partial Reconfiguration
- Physical Unclonable Functions