On chip reconfigurable CMOS analog circuit design and automation against aging phenomena: Sense and react

Performance of analog circuits degrades over time due to several time-dependent degradation mechanisms. Due to the increased aging problems in ever-shrinking dimensions, reliability of complementary metal-oxide-semiconductor analog circuits has become a major concern. Overdesign is a popular aging-aware circuit design approach, where circuit operation is guardbanded by choosing the design point beyond the optimal region. For the sake of reliability, power consumption and chip area are sacrificed in this approach, which is undesirable considering strict energy limitations in modern applications. Conversely, Sense and React (S&R) approach serves the same purpose without any additional power consumption, in which degradation of circuit features is detected by online monitoring and recovered immediately. Furthermore, such systems enable remote control and healing of circuits. However, design of an S&R system is quite complicated. In particular, determination of efficient aging signatures and design of recovery strategy are highly challenging problems. This study thoroughly discusses the design process of S&R systems and proposes computer-aided-design-based design strategies that reduce the designer effort considerably. A novel design automation tool for S&R systems was developed, in which signature selection and recovery determination were integrated. To demonstrate proposed design strategies, two different S&R systems are implemented, simulated, and discussed in detail.