Multiplier-less 1-level discrete wavelet transform implementations on ZC706 development kit

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Citations (Scopus)

Abstract

In this paper, we investigate the design and implementation aspects of 1-level DWT by employing a finite impulse response (FIR) filter on FPGA platform. We estimate the performance requirements and hardware resources for two key multiplication-free architectures, namely, distributed arithmetic algorithm (DAA) and residue number system (RNS), allowing for selection of the proper algorithm and implementation of DAA and RNS-based DWT. The design has been implemented and synthesized in Xilinx ZYNQ-7000 FPGA, taking advantage of embedded block RAMs (BRAMs). The results show that the DAA-based approach is appropriate and feasible for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps.

Original languageEnglish
Title of host publication2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1122-1126
Number of pages5
ISBN (Electronic)9786050107371
Publication statusPublished - 2 Jul 2017
Event10th International Conference on Electrical and Electronics Engineering, ELECO 2017 - Bursa, Turkey
Duration: 29 Nov 20172 Dec 2017

Publication series

Name2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017
Volume2018-January

Conference

Conference10th International Conference on Electrical and Electronics Engineering, ELECO 2017
Country/TerritoryTurkey
CityBursa
Period29/11/172/12/17

Bibliographical note

Publisher Copyright:
© 2017 EMO (Turkish Chamber of Electrical Enginners).

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