Abstract
In this paper, we investigate the design and implementation aspects of 1-level DWT by employing a finite impulse response (FIR) filter on FPGA platform. We estimate the performance requirements and hardware resources for two key multiplication-free architectures, namely, distributed arithmetic algorithm (DAA) and residue number system (RNS), allowing for selection of the proper algorithm and implementation of DAA and RNS-based DWT. The design has been implemented and synthesized in Xilinx ZYNQ-7000 FPGA, taking advantage of embedded block RAMs (BRAMs). The results show that the DAA-based approach is appropriate and feasible for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps.
Original language | English |
---|---|
Title of host publication | 2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1122-1126 |
Number of pages | 5 |
ISBN (Electronic) | 9786050107371 |
Publication status | Published - 2 Jul 2017 |
Event | 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 - Bursa, Turkey Duration: 29 Nov 2017 → 2 Dec 2017 |
Publication series
Name | 2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
---|---|
Volume | 2018-January |
Conference
Conference | 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
---|---|
Country/Territory | Turkey |
City | Bursa |
Period | 29/11/17 → 2/12/17 |
Bibliographical note
Publisher Copyright:© 2017 EMO (Turkish Chamber of Electrical Enginners).