Abstract
In this paper, the first generalization for time-delay sampled-data chaotic system in order to generate multi-scroll attractor is introduced with its circuit implementation. An efficient delay-line with binary priority encoding, parallel shifting, and binary decoding is also suggested and implemented to overcome the delay line realization drawback in such systems. The proposed system enhances the complexity of chaotic behavior by means of multi-scroll feature and exemplifies the simplification of chaotic systems for better realizations.
Original language | English |
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Pages (from-to) | 1263-1276 |
Number of pages | 14 |
Journal | International Journal of Circuit Theory and Applications |
Volume | 44 |
Issue number | 6 |
DOIs | |
Publication status | Published - 1 Jun 2016 |
Bibliographical note
Publisher Copyright:Copyright © 2015 John Wiley & Sons, Ltd.
Keywords
- chaos
- chaotic attractor
- delay
- delay line
- FPGA
- multi-scroll
- priority encoder