Modeling n/spl times/n bit multiplication blocks for DSP applications using VHDL

In this paper we propose two models of multiplication blocks by using VHDL. The algorithms that are used for writing the models are suitable for high speed multiplication and have regular cellular array structures. We have simplified some equations given in the references and then have written the VHDL model accordingly. Thus, a circuit synthesized by using the models proposed in this paper will have less area and gate count on the longest path than those given in the literature. We propose explicit expressions for calculating area values and the gate count on the longest path of the circuits for both of multiplication blocks for any value of n for, 2/spl les/n/spl les/54. Also we propose a method to determine the types of gates on the longest path of the circuit.