Model-based variation-aware integrated circuit design

Ting Zhu; Mustafa Berke Yelten; Michael B. Steer; Paul D. Franzon

doi:10.1007/978-1-4614-7551-4_8

Model-based variation-aware integrated circuit design

Ting Zhu^*, Mustafa Berke Yelten, Michael B. Steer, Paul D. Franzon

^*Corresponding author for this work

North Carolina State University

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

Abstract

Modern integrated circuit designers must deal with complex design and simulation problems while coping with large device to device parametric variations and often imperfect information. This chapter presents surrogate model-based methods to generate circuit performance models for design, device models, and high-speed input-output (IO) buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. The variation-aware IO buffer macromodel integrates surrogate modeling and a physically based model structure. The new IO macromodel provides both good accuracy and scalability for signal integrity analysis.

Original language	English
Title of host publication	Surrogate-Based Modeling and Optimization
Subtitle of host publication	Applications in Engineering
Publisher	Springer New York
Pages	171-188
Number of pages	18
Volume	9781461475514
ISBN (Electronic)	9781461475514
ISBN (Print)	1461475503, 9781461475507
DOIs	https://doi.org/10.1007/978-1-4614-7551-4_8
Publication status	Published - 1 Aug 2013
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2013 Springer Science+Business Media New York. All rights are reserved.

Keywords

Circuit optimization
Design aids
Design exploration
Device model
IO model
Integrated circuit
Model-based design
Performance model
Self-calibrated circuit
Surrogate modeling
Variation aware
Yield analysis

Access to Document

10.1007/978-1-4614-7551-4_8

Cite this

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Model-based variation-aware integrated circuit design

Abstract

Bibliographical note

Keywords

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