Model-Based FPGA AI Accelerator Design Using Vitis AI with In-Depth Performance and Energy Efficiency Analysis

This paper presents a model-based design of AI accelerator following the Vitis TRD flow, implemented on the AMD Kria KV260 Vision AI Starter Kit. The ResNet-18 model, developed in PyTorch, was quantized, compiled with Vitis AI, and deployed to the FPGA via PYNQ. We deeply analyzed different DPU configurations and frequencies, focusing on resource utilization, power, FPS, and energy efficiency. Results show that resource utilization remains constant across frequencies, but lower frequencies increase energy consumption. For optimal performance and energy efficiency, high-MAC DPU configurations should be used at higher frequencies. To our knowledge, no prior research has fully detailed the Vitis TRD flow within Vitis AI. Most rely on Vivado TRD, which requires PetaLinux. This work offers a comprehensive guide for deploying AI models on FPGAs using Ubuntu, eliminating the need for PetaLinux expertise.