Integrated synthesis methodology for crossbar arrays

M. Ceylan Morgul; Onur Tunali; Mustafa Altun; Luca Frontini; Valentina Ciriani; E. Ioana Vatajelu; Lorena Anghel; Csaba Andras Moritz; Mircea R. Stan; Dan Alexandrescu

doi:10.1145/3232195.3232211

Integrated synthesis methodology for crossbar arrays

M. Ceylan Morgul, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, E. Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan, Dan Alexandrescu

Department of Electronics and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Citations (Scopus)

Abstract

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.

Original language	English
Title of host publication	Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018
Publisher	Association for Computing Machinery, Inc
Pages	91-97
Number of pages	7
ISBN (Electronic)	9781450358156
DOIs	https://doi.org/10.1145/3232195.3232211
Publication status	Published - 17 Jul 2018
Event	14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018 - Athens, Greece Duration: 18 Jul 2018 → 19 Jul 2018

Publication series

Name	Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018

Conference

Conference	14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018
Country/Territory	Greece
City	Athens
Period	18/07/18 → 19/07/18

Bibliographical note

Publisher Copyright:
© 2018 Association for Computing Machinery.

Funding

This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement #691178, as well as supported by the TUBITAK-Career project #113E760.

Funders	Funder number
European Union’s H2020 research and innovation programme	113E760
Horizon 2020 Framework Programme	691178

Keywords

Crossbar Arrays
Defect Tolerance
Fault Tolerance
Logic Synthesis
Memristor Arrays
Performance Optimization

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1145/3232195.3232211

Cite this

Ceylan Morgul, M., Tunali, O., Altun, M., Frontini, L., Ciriani, V., Ioana Vatajelu, E., Anghel, L., Moritz, C. A., Stan, M. R., & Alexandrescu, D. (2018). Integrated synthesis methodology for crossbar arrays. In Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018 (pp. 91-97). (Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018). Association for Computing Machinery, Inc. https://doi.org/10.1145/3232195.3232211

Ceylan Morgul, M. ; Tunali, Onur ; Altun, Mustafa et al. / Integrated synthesis methodology for crossbar arrays. Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. Association for Computing Machinery, Inc, 2018. pp. 91-97 (Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018).

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abstract = "Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.",

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Ceylan Morgul, M, Tunali, O, Altun, M, Frontini, L, Ciriani, V, Ioana Vatajelu, E, Anghel, L, Moritz, CA, Stan, MR & Alexandrescu, D 2018, Integrated synthesis methodology for crossbar arrays. in Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018, Association for Computing Machinery, Inc, pp. 91-97, 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018, Athens, Greece, 18/07/18. https://doi.org/10.1145/3232195.3232211

Integrated synthesis methodology for crossbar arrays. / Ceylan Morgul, M.; Tunali, Onur; Altun, Mustafa et al.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. Association for Computing Machinery, Inc, 2018. p. 91-97 (Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Altun, Mustafa

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AU - Anghel, Lorena

AU - Moritz, Csaba Andras

AU - Stan, Mircea R.

AU - Alexandrescu, Dan

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AB - Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.

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Ceylan Morgul M, Tunali O, Altun M, Frontini L, Ciriani V, Ioana Vatajelu E et al. Integrated synthesis methodology for crossbar arrays. In Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. Association for Computing Machinery, Inc. 2018. p. 91-97. (Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018). doi: 10.1145/3232195.3232211

Integrated synthesis methodology for crossbar arrays

Abstract

Publication series

Conference

Bibliographical note

Funding

Keywords

UN SDGs

Access to Document

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