Improving the bandwidth of the transimpedance amplifier based on CS stages in cascode configuration using impedance matching techniques

Jawdat Y. Abu-Taha; Metin Yazgi

doi:10.1007/s10470-016-0757-6

Improving the bandwidth of the transimpedance amplifier based on CS stages in cascode configuration using impedance matching techniques

Jawdat Y. Abu-Taha^*, Metin Yazgi

^*Corresponding author for this work

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

This paper describes a matching technique to improve the bandwidth of multi-GHz frequency ranges for the transimpedance amplifier. It is shown that by simultaneously using of series input matching topology and T-output matching network, the bandwidth of the TIA can be obviously improved. This methodology is supported by a design example in a 0.18 μm CMOS technology. The post layout simulation results show a −3dB bandwidth of 20 GHz with 50 fF photodiode capacitance, a transimpedance gain of 52.6dBΩ, 11pA/Hz input referred noise and group delay less than 8.3ps. The TIA dissipates 1.3mW from a 1.8V supply voltage.

Original language	English
Pages (from-to)	685-691
Number of pages	7
Journal	Analog Integrated Circuits and Signal Processing
Volume	89
Issue number	3
DOIs	https://doi.org/10.1007/s10470-016-0757-6
Publication status	Published - 1 Dec 2016

Bibliographical note

Publisher Copyright:
© 2016, Springer Science+Business Media New York.

Keywords

Bandwidth extension
Cascode stage
Input-referred noise
Matching network
Transimpedance amplifier (TIA)

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10.1007/s10470-016-0757-6

Cite this

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abstract = "This paper describes a matching technique to improve the bandwidth of multi-GHz frequency ranges for the transimpedance amplifier. It is shown that by simultaneously using of series input matching topology and T-output matching network, the bandwidth of the TIA can be obviously improved. This methodology is supported by a design example in a 0.18 μm CMOS technology. The post layout simulation results show a −3dB bandwidth of 20 GHz with 50 fF photodiode capacitance, a transimpedance gain of 52.6dBΩ, 11pA/Hz input referred noise and group delay less than 8.3ps. The TIA dissipates 1.3mW from a 1.8V supply voltage.",

keywords = "Bandwidth extension, Cascode stage, Input-referred noise, Matching network, Transimpedance amplifier (TIA)",

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N2 - This paper describes a matching technique to improve the bandwidth of multi-GHz frequency ranges for the transimpedance amplifier. It is shown that by simultaneously using of series input matching topology and T-output matching network, the bandwidth of the TIA can be obviously improved. This methodology is supported by a design example in a 0.18 μm CMOS technology. The post layout simulation results show a −3dB bandwidth of 20 GHz with 50 fF photodiode capacitance, a transimpedance gain of 52.6dBΩ, 11pA/Hz input referred noise and group delay less than 8.3ps. The TIA dissipates 1.3mW from a 1.8V supply voltage.

AB - This paper describes a matching technique to improve the bandwidth of multi-GHz frequency ranges for the transimpedance amplifier. It is shown that by simultaneously using of series input matching topology and T-output matching network, the bandwidth of the TIA can be obviously improved. This methodology is supported by a design example in a 0.18 μm CMOS technology. The post layout simulation results show a −3dB bandwidth of 20 GHz with 50 fF photodiode capacitance, a transimpedance gain of 52.6dBΩ, 11pA/Hz input referred noise and group delay less than 8.3ps. The TIA dissipates 1.3mW from a 1.8V supply voltage.

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Improving the bandwidth of the transimpedance amplifier based on CS stages in cascode configuration using impedance matching techniques

Abstract

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Keywords

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