Abstract
Software defined radio (SDR) applications are usually preferred in low power flexible communication systems. In this paper, a software defined Frequency Modulation (FM) demodulator is presented. Mixed demodulation technique is used to build a digital FM demodulator which has 16 MHz sampling rate. Proposed system was implemented successfully on a Field Programmable Gate Array (FPGA). The system uses 1247 logic elements. FPGA's power consumption is 113.56 mW. The system was tested and verified with a test bed including Analog Digital Converter (ADC) and Digital Analog Converter (DAC).
| Original language | English |
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| Title of host publication | 2015 23rd Telecommunications Forum, TELFOR 2015 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 333-336 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781509000548 |
| DOIs | |
| Publication status | Published - 8 Jan 2016 |
| Event | 23rd Telecommunications Forum, TELFOR 2015 - Belgrade, Serbia Duration: 24 Nov 2015 → 26 Nov 2015 |
Publication series
| Name | 2015 23rd Telecommunications Forum, TELFOR 2015 |
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Conference
| Conference | 23rd Telecommunications Forum, TELFOR 2015 |
|---|---|
| Country/Territory | Serbia |
| City | Belgrade |
| Period | 24/11/15 → 26/11/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- CORDIC
- Digital FM
- FPGA
- SDR