Implementation of a PUF circuit on a FPGA

Mehmet Soybali*, Berna Ors, Gokay Saldamli

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Citations (Scopus)

Abstract

Having a robust and tamper proof structure, recently proposed pyhsical unclonable functions (PUF) are considered as a promising instrument that would be used for secure key generation and storage, integrated circuit (IC) authentication and generating chip-unique signatures. We describe a delay-based PUF architecture suitable for RFID devices mostly suffer from low computational power and tiny sillicon area. In order to match these constraints, we design a mux and an arbiter based PUF circuit that is implemented on an Field Programmable Gate Array (FPGA) for experimental purposes. Based on our measurements which is extended to variable environmental conditions, we state the length of a reliable PUF circuit.

Original languageEnglish
Title of host publication2011 4th IFIP International Conference on New Technologies, Mobility and Security, NTMS 2011 - Proceedings
DOIs
Publication statusPublished - 2011
Event4th IFIP International Conference on New Technologies, Mobility and Security, NTMS 2011 - Paris, France
Duration: 7 Feb 201110 Feb 2011

Publication series

Name2011 4th IFIP International Conference on New Technologies, Mobility and Security, NTMS 2011 - Proceedings

Conference

Conference4th IFIP International Conference on New Technologies, Mobility and Security, NTMS 2011
Country/TerritoryFrance
CityParis
Period7/02/1110/02/11

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