Abstract
Security is one of the most important design parameters in communication systems. Security of cryptographic systems depends on the unpredictability of keys. Chaotic random number generators have become an alternative method for random number generation instead of physical noise based ones. In this work, we describe a system-on-chip design which includes a chaos-based random number generator. Key generation, encryption-decryption blocks and control unit are designed to run on the same chip. All blocks are connected to the Microblaze softcore processor and implemented on a Xilinx FPGA. Structural details of the system and the results are shared.
Original language | English |
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Title of host publication | 2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1277-1280 |
Number of pages | 4 |
ISBN (Electronic) | 9786050107371 |
Publication status | Published - 2 Jul 2017 |
Event | 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 - Bursa, Turkey Duration: 29 Nov 2017 → 2 Dec 2017 |
Publication series
Name | 2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
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Volume | 2018-January |
Conference
Conference | 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
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Country/Territory | Turkey |
City | Bursa |
Period | 29/11/17 → 2/12/17 |
Bibliographical note
Publisher Copyright:© 2017 EMO (Turkish Chamber of Electrical Enginners).