Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi

Hakan Aktaş; Refik Sever; Behçet Uʇur Töreyin

doi:10.1109/SIU.2015.7130315

Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi

Translated title of the contribution: A two stage template matching algorithm and its Implementation on FPGA

Hakan Aktaş, Refik Sever, Behçet Uʇur Töreyin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.

Translated title of the contribution	A two stage template matching algorithm and its Implementation on FPGA
Original language	Turkish
Title of host publication	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2214-2217
Number of pages	4
ISBN (Electronic)	9781467373869
DOIs	https://doi.org/10.1109/SIU.2015.7130315
Publication status	Published - 19 Jun 2015
Externally published	Yes
Event	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Malatya, Turkey Duration: 16 May 2015 → 19 May 2015

Publication series

Name	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

Conference

Conference	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015
Country/Territory	Turkey
City	Malatya
Period	16/05/15 → 19/05/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Access to Document

10.1109/SIU.2015.7130315

Cite this

Aktaş, H., Sever, R., & Töreyin, B. U. (2015). Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. In 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings (pp. 2214-2217). Article 7130315 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIU.2015.7130315

Aktaş, Hakan ; Sever, Refik ; Töreyin, Behçet Uʇur. / Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 2214-2217 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings).

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title = "Iki A{\c s}amali {\c S}ablon E{\c s}le{\c s}tirme Algoritmasi ve Y{\"u}ksek Hizli FPGA Ger{\c c}eklemesi",

abstract = "In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.",

keywords = "Field-Programmable-Gate-Array (FPGA), Memorry Adressing, Parallel Processing, Sum of Absolute Differences, Template Matching, Unmanned Air Vehicle (UAV)",

author = "Hakan Akta{\c s} and Refik Sever and T{\"o}reyin, {Beh{\c c}et Uʇur}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 ; Conference date: 16-05-2015 Through 19-05-2015",

year = "2015",

month = jun,

day = "19",

doi = "10.1109/SIU.2015.7130315",

language = "T{\"u}rk{\c c}e",

series = "2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Aktaş, H, Sever, R & Töreyin, BU 2015, Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. in 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings., 7130315, 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 2214-2217, 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015, Malatya, Turkey, 16/05/15. https://doi.org/10.1109/SIU.2015.7130315

Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. / Aktaş, Hakan; Sever, Refik; Töreyin, Behçet Uʇur.
2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2214-2217 7130315 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi

AU - Aktaş, Hakan

AU - Sever, Refik

AU - Töreyin, Behçet Uʇur

PY - 2015/6/19

Y1 - 2015/6/19

N2 - In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.

AB - In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.

KW - Field-Programmable-Gate-Array (FPGA)

KW - Memorry Adressing

KW - Parallel Processing

KW - Sum of Absolute Differences

KW - Template Matching

KW - Unmanned Air Vehicle (UAV)

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U2 - 10.1109/SIU.2015.7130315

DO - 10.1109/SIU.2015.7130315

M3 - Konferans katkısı

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T3 - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

SP - 2214

EP - 2217

BT - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015

Y2 - 16 May 2015 through 19 May 2015

ER -

Aktaş H, Sever R, Töreyin BU. Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. In 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2015. p. 2214-2217. 7130315. (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings). doi: 10.1109/SIU.2015.7130315

Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi

Abstract

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