Abstract
In this paper, a complementary filter for pitch and roll angle estimation based on linear acceleration and angular rate is designed and implemented on a Xilinx Zynq System on Chip (SoC) device. The filter is partitioned into two parts as hardware (HW) and software (SW) as a result of the communication performance analysis of Advanced eXtensible Interface (AXI) bus for a parallel interface in the Programmable Logic (PL) part of the SoC. PetaLinux operates on the Processing System (PS) part of the SoC and runs a C application. PL performs the HW abstraction by transforming serial inputs/outputs with noise rejection filters into memory mapped variables. Real-time test results and SoC utilization results are reported.
Original language | English |
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Title of host publication | 2020 7th International Conference on Electrical and Electronics Engineering, ICEEE 2020 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 351-354 |
Number of pages | 4 |
ISBN (Electronic) | 9781728167886 |
DOIs | |
Publication status | Published - Apr 2020 |
Event | 7th International Conference on Electrical and Electronics Engineering, ICEEE 2020 - Antalya, Turkey Duration: 14 Apr 2020 → 16 Apr 2020 |
Publication series
Name | 2020 7th International Conference on Electrical and Electronics Engineering, ICEEE 2020 |
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Conference
Conference | 7th International Conference on Electrical and Electronics Engineering, ICEEE 2020 |
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Country/Territory | Turkey |
City | Antalya |
Period | 14/04/20 → 16/04/20 |
Bibliographical note
Publisher Copyright:© 2020 IEEE.
Keywords
- filter
- HW/SW codesign
- Linux
- System on chip
- Zynq