Hardware implementation of an elliptic curve processor over GF(p)

Siddika Berna Örs; Lejla Batina; Bart Preneel; Joos Vandewalle

doi:10.1109/ASAP.2003.1212866

Hardware implementation of an elliptic curve processor over GF(p)

Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

70 Citations (SciVal)

Abstract

We describe a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC), i.e., elliptic curve (EC) and RSA cryptosystems. Montgomery modular multiplication in a systolic array architecture is used for modular multiplication. The processor consists of special operational blocks for Montgomery modular multiplication, modular addition/subtraction, EC point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.

Original language	English
Title of host publication	Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003
Editors	Ed Deprettere, Shuvra Bhattacharyya, Joseph Cavallaro, Alain Darte, Lothar Thiele
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	433-443
Number of pages	11
ISBN (Electronic)	076951992X
DOIs	https://doi.org/10.1109/ASAP.2003.1212866
Publication status	Published - 2003
Externally published	Yes
Event	IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003 - The Hague, Netherlands Duration: 24 Jun 2003 → 26 Jun 2003

Publication series

Name	Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume	2003-January
ISSN (Print)	2160-0511
ISSN (Electronic)	2160-052X

Conference

Conference	IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003
Country/Territory	Netherlands
City	The Hague
Period	24/06/03 → 26/06/03

Bibliographical note

Publisher Copyright:
© 2003 IEEE.

Keywords

Elliptic Curve Cryptosystems
FPGA
Modular Operations

Access to Document

10.1109/ASAP.2003.1212866

Cite this

Örs, S. B., Batina, L., Preneel, B., & Vandewalle, J. (2003). Hardware implementation of an elliptic curve processor over GF(p). In E. Deprettere, S. Bhattacharyya, J. Cavallaro, A. Darte, & L. Thiele (Eds.), Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003 (pp. 433-443). Article 1212866 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2003.1212866

Örs, Siddika Berna ; Batina, Lejla ; Preneel, Bart et al. / Hardware implementation of an elliptic curve processor over GF(p). Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003. editor / Ed Deprettere ; Shuvra Bhattacharyya ; Joseph Cavallaro ; Alain Darte ; Lothar Thiele. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 433-443 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).

@inproceedings{7940e6f6b6f44c969ac0e0b14f789a24,

title = "Hardware implementation of an elliptic curve processor over GF(p)",

abstract = "We describe a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC), i.e., elliptic curve (EC) and RSA cryptosystems. Montgomery modular multiplication in a systolic array architecture is used for modular multiplication. The processor consists of special operational blocks for Montgomery modular multiplication, modular addition/subtraction, EC point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.",

keywords = "Elliptic Curve Cryptosystems, FPGA, Modular Operations",

author = "{\"O}rs, \{Siddika Berna\} and Lejla Batina and Bart Preneel and Joos Vandewalle",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003 ; Conference date: 24-06-2003 Through 26-06-2003",

year = "2003",

doi = "10.1109/ASAP.2003.1212866",

language = "English",

series = "Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "433--443",

editor = "Ed Deprettere and Shuvra Bhattacharyya and Joseph Cavallaro and Alain Darte and Lothar Thiele",

booktitle = "Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003",

address = "United States",

}

Örs, SB, Batina, L, Preneel, B & Vandewalle, J 2003, Hardware implementation of an elliptic curve processor over GF(p). in E Deprettere, S Bhattacharyya, J Cavallaro, A Darte & L Thiele (eds), Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003., 1212866, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 433-443, IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003, The Hague, Netherlands, 24/06/03. https://doi.org/10.1109/ASAP.2003.1212866

Hardware implementation of an elliptic curve processor over GF(p). / Örs, Siddika Berna; Batina, Lejla; Preneel, Bart et al.
Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003. ed. / Ed Deprettere; Shuvra Bhattacharyya; Joseph Cavallaro; Alain Darte; Lothar Thiele. Institute of Electrical and Electronics Engineers Inc., 2003. p. 433-443 1212866 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Hardware implementation of an elliptic curve processor over GF(p)

AU - Örs, Siddika Berna

AU - Batina, Lejla

AU - Preneel, Bart

AU - Vandewalle, Joos

PY - 2003

Y1 - 2003

N2 - We describe a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC), i.e., elliptic curve (EC) and RSA cryptosystems. Montgomery modular multiplication in a systolic array architecture is used for modular multiplication. The processor consists of special operational blocks for Montgomery modular multiplication, modular addition/subtraction, EC point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.

AB - We describe a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC), i.e., elliptic curve (EC) and RSA cryptosystems. Montgomery modular multiplication in a systolic array architecture is used for modular multiplication. The processor consists of special operational blocks for Montgomery modular multiplication, modular addition/subtraction, EC point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.

KW - Elliptic Curve Cryptosystems

KW - FPGA

KW - Modular Operations

UR - https://www.scopus.com/pages/publications/84942517531

U2 - 10.1109/ASAP.2003.1212866

DO - 10.1109/ASAP.2003.1212866

M3 - Conference contribution

AN - SCOPUS:84942517531

T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

SP - 433

EP - 443

BT - Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003

A2 - Deprettere, Ed

A2 - Bhattacharyya, Shuvra

A2 - Cavallaro, Joseph

A2 - Darte, Alain

A2 - Thiele, Lothar

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003

Y2 - 24 June 2003 through 26 June 2003

ER -

Örs SB, Batina L, Preneel B, Vandewalle J. Hardware implementation of an elliptic curve processor over GF(p). In Deprettere E, Bhattacharyya S, Cavallaro J, Darte A, Thiele L, editors, Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 433-443. 1212866. (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors). doi: 10.1109/ASAP.2003.1212866

Hardware implementation of an elliptic curve processor over GF(p)

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this