Hardware implementation of a Montgomery modular multiplier in a systolic array

Siddika Berna Örs; Lejla Batina; Bart Preneel; Joos Vandewalle

doi:10.1109/IPDPS.2003.1213341

Hardware implementation of a Montgomery modular multiplier in a systolic array

Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

46 Citations (Scopus)

Abstract

This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC) i.e. ECC and RSA cryptosystems. The challenge of current PKC implementations is to deal with long numbers (160-2048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of repeated modular multiplications, which is also the basic operation for ECC protocols. The solution proposed in this work uses a systolic array implementation and can be used for arbitrary precisions. We also present modular exponentiation based on Montgomery's Multiplication Method (MMM).

Original language	English
Title of host publication	Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	0769519261, 9780769519265
DOIs	https://doi.org/10.1109/IPDPS.2003.1213341
Publication status	Published - 2003
Externally published	Yes
Event	International Parallel and Distributed Processing Symposium, IPDPS 2003 - Nice, France Duration: 22 Apr 2003 → 26 Apr 2003

Publication series

Name	Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Conference

Conference	International Parallel and Distributed Processing Symposium, IPDPS 2003
Country/Territory	France
City	Nice
Period	22/04/03 → 26/04/03

Bibliographical note

Publisher Copyright:
© 2003 IEEE.

Keywords

ECC
FPGA
Montgomery's Multiplication Method
Public Key Cryptography
RSA
Systolic array

Access to Document

10.1109/IPDPS.2003.1213341

Cite this

Örs, S. B., Batina, L., Preneel, B., & Vandewalle, J. (2003). Hardware implementation of a Montgomery modular multiplier in a systolic array. In Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003 Article 1213341 (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPS.2003.1213341

Örs, Siddika Berna ; Batina, Lejla ; Preneel, Bart et al. / Hardware implementation of a Montgomery modular multiplier in a systolic array. Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc., 2003. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003).

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abstract = "This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC) i.e. ECC and RSA cryptosystems. The challenge of current PKC implementations is to deal with long numbers (160-2048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of repeated modular multiplications, which is also the basic operation for ECC protocols. The solution proposed in this work uses a systolic array implementation and can be used for arbitrary precisions. We also present modular exponentiation based on Montgomery's Multiplication Method (MMM).",

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Örs, SB, Batina, L, Preneel, B & Vandewalle, J 2003, Hardware implementation of a Montgomery modular multiplier in a systolic array. in Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003., 1213341, Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003, Institute of Electrical and Electronics Engineers Inc., International Parallel and Distributed Processing Symposium, IPDPS 2003, Nice, France, 22/04/03. https://doi.org/10.1109/IPDPS.2003.1213341

Hardware implementation of a Montgomery modular multiplier in a systolic array. / Örs, Siddika Berna; Batina, Lejla; Preneel, Bart et al.
Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc., 2003. 1213341 (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Örs SB, Batina L, Preneel B, Vandewalle J. Hardware implementation of a Montgomery modular multiplier in a systolic array. In Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc. 2003. 1213341. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003). doi: 10.1109/IPDPS.2003.1213341

Hardware implementation of a Montgomery modular multiplier in a systolic array

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