Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm

Hakan Çetinkaya; Alper Girgin; Tufan Coskun Karalar

doi:10.1016/j.mejo.2023.105840

Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm

Hakan Çetinkaya^*, Alper Girgin, Tufan Coskun Karalar

^*Corresponding author for this work

Department of Electronics and Communication Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

This work presents a novel multi voltage level non-overlapping clock phase generation architecture with a differential clock driver. It has a compact fully integrated power management, including LDOs and bandgap reference circuit. It is capable of controlling the PVT variation via SPI programming. It is functional from 50 MHz up to 1 GHz, to be used for pipelined ADCs. The core chip achieves SNR_jitter around 72 dB from 50 MHz to 150 MHz, and above 68 dB from 150 MHz to 400 MHz, above 60 dB up to 1 GHz clock signals. The core section consumes 19 mA at 1 GHz from an external supply of 3 V. The chip occupies 1235 μm × 1300 μm, in a SiGe BiCMOS 0.13 μm process. The clock generation system occupies 400 μm × 360 μm silicon area, excluding I/O pads and interface circuits. It is packed in a 5 mm × 5 mm QFN32 package and assembled onto an FR4 board.

Original language	English
Article number	105840
Journal	Microelectronics Journal
Volume	139
DOIs	https://doi.org/10.1016/j.mejo.2023.105840
Publication status	Published - Sept 2023

Bibliographical note

Publisher Copyright:
© 2023

Funding

This work is financially supported by the Scientific and Technological Research Council of Turkey (TÜBİTAK) for the partial fulfilment of the project TÜBİTAK-1003, 115E752.

Funders	Funder number
Türkiye Bilimsel ve Teknolojik Araştırma Kurumu	TÜBİTAK-1003, 115E752

Keywords

Clock level shifter
Differential to single ended converter
FR4
LDOs
Non-overlapping clock generation
QFN32

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10.1016/j.mejo.2023.105840

Cite this

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title = "Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm",

abstract = "This work presents a novel multi voltage level non-overlapping clock phase generation architecture with a differential clock driver. It has a compact fully integrated power management, including LDOs and bandgap reference circuit. It is capable of controlling the PVT variation via SPI programming. It is functional from 50 MHz up to 1 GHz, to be used for pipelined ADCs. The core chip achieves SNRjitter around 72 dB from 50 MHz to 150 MHz, and above 68 dB from 150 MHz to 400 MHz, above 60 dB up to 1 GHz clock signals. The core section consumes 19 mA at 1 GHz from an external supply of 3 V. The chip occupies 1235 μm × 1300 μm, in a SiGe BiCMOS 0.13 μm process. The clock generation system occupies 400 μm × 360 μm silicon area, excluding I/O pads and interface circuits. It is packed in a 5 mm × 5 mm QFN32 package and assembled onto an FR4 board.",

keywords = "Clock level shifter, Differential to single ended converter, FR4, LDOs, Non-overlapping clock generation, QFN32",

author = "Hakan {\c C}etinkaya and Alper Girgin and Karalar, {Tufan Coskun}",

note = "Publisher Copyright: {\textcopyright} 2023",

year = "2023",

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doi = "10.1016/j.mejo.2023.105840",

language = "English",

volume = "139",

journal = "Microelectronics Journal",

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AU - Çetinkaya, Hakan

AU - Girgin, Alper

AU - Karalar, Tufan Coskun

PY - 2023/9

Y1 - 2023/9

N2 - This work presents a novel multi voltage level non-overlapping clock phase generation architecture with a differential clock driver. It has a compact fully integrated power management, including LDOs and bandgap reference circuit. It is capable of controlling the PVT variation via SPI programming. It is functional from 50 MHz up to 1 GHz, to be used for pipelined ADCs. The core chip achieves SNRjitter around 72 dB from 50 MHz to 150 MHz, and above 68 dB from 150 MHz to 400 MHz, above 60 dB up to 1 GHz clock signals. The core section consumes 19 mA at 1 GHz from an external supply of 3 V. The chip occupies 1235 μm × 1300 μm, in a SiGe BiCMOS 0.13 μm process. The clock generation system occupies 400 μm × 360 μm silicon area, excluding I/O pads and interface circuits. It is packed in a 5 mm × 5 mm QFN32 package and assembled onto an FR4 board.

AB - This work presents a novel multi voltage level non-overlapping clock phase generation architecture with a differential clock driver. It has a compact fully integrated power management, including LDOs and bandgap reference circuit. It is capable of controlling the PVT variation via SPI programming. It is functional from 50 MHz up to 1 GHz, to be used for pipelined ADCs. The core chip achieves SNRjitter around 72 dB from 50 MHz to 150 MHz, and above 68 dB from 150 MHz to 400 MHz, above 60 dB up to 1 GHz clock signals. The core section consumes 19 mA at 1 GHz from an external supply of 3 V. The chip occupies 1235 μm × 1300 μm, in a SiGe BiCMOS 0.13 μm process. The clock generation system occupies 400 μm × 360 μm silicon area, excluding I/O pads and interface circuits. It is packed in a 5 mm × 5 mm QFN32 package and assembled onto an FR4 board.

KW - Clock level shifter

KW - Differential to single ended converter

KW - FR4

KW - LDOs

KW - Non-overlapping clock generation

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Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm

Abstract

Bibliographical note

Funding

Keywords

Access to Document

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