Skip to main navigation Skip to search Skip to main content

Fully Active Meminductor Emulator Circuit

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)

Abstract

This work introduces an active-only architecture for a meminductor emulator, where the required capacitive behavior is derived solely from the inherent gate capacitances of MOS devices, removing the need for any external capacitors. By avoiding passive elements, the proposed approach notably decreases the silicon area demanded in IC implementations. Validation through Cadence-based simulations using a 0.18 μm CMOS process demonstrates that the practical behavior of the circuit aligns well with the theoretical model and confirms its viability.

Original languageEnglish
Title of host publication2025 16th International Conference on Electrical and Electronics Engineering, ELECO 2025
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798331546946
DOIs
Publication statusPublished - 2025
Event2025 16th International Conference on Electrical and Electronics Engineering, ELECO 2025 - Istanbul, Turkey
Duration: 27 Nov 202529 Nov 2025

Publication series

Name2025 16th International Conference on Electrical and Electronics Engineering, ELECO 2025

Conference

Conference2025 16th International Conference on Electrical and Electronics Engineering, ELECO 2025
Country/TerritoryTurkey
CityIstanbul
Period27/11/2529/11/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

  • Active meminductor architecture
  • Intrinsic-capacitance-based design
  • Memory characteristics

Fingerprint

Dive into the research topics of 'Fully Active Meminductor Emulator Circuit'. Together they form a unique fingerprint.

Cite this