Full digital implementation of a chaotic time-delay sampled-data system

Chaos-based RNGs have become an alternative method for random number generation (RNG) which is the vital part of the security hardware. When full-digital implementations of a chaotic system are considered, a periodic limit cycle with a large period appears. In order to reverse this degradation in dynamics of chaotic time-delay sampled system, the digital circuit has been supported by delaying buffers which utilize the jitter to break the periodic motion. Thus, the a periodic behavior of proposed full digital design resembles the original chaotic behavior. Designs of the system are tested on a field-programmable gate array (FPGA). Furthermore, two RNGs based on these designs are given and test results are presented in the paper. Tests indicate that when time-varying delay is included using propagation delay even 8-bit representation of the system shows the sensitive dependence on initial conditions.