Full digital implementation of a chaotic time-delay sampled-data system

R. Yeniceri, A. Vardar, M. E. Yalcm

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)

Abstract

Chaos-based RNGs have become an alternative method for random number generation (RNG) which is the vital part of the security hardware. When full-digital implementations of a chaotic system are considered, a periodic limit cycle with a large period appears. In order to reverse this degradation in dynamics of chaotic time-delay sampled system, the digital circuit has been supported by delaying buffers which utilize the jitter to break the periodic motion. Thus, the a periodic behavior of proposed full digital design resembles the original chaotic behavior. Designs of the system are tested on a field-programmable gate array (FPGA). Furthermore, two RNGs based on these designs are given and test results are presented in the paper. Tests indicate that when time-varying delay is included using propagation delay even 8-bit representation of the system shows the sensitive dependence on initial conditions.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
Publication statusPublished - 25 Sept 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: 28 May 201731 May 2017

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country/TerritoryUnited States
CityBaltimore
Period28/05/1731/05/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

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