Abstract
Chaos-based RNGs have become an alternative method for random number generation (RNG) which is the vital part of the security hardware. When full-digital implementations of a chaotic system are considered, a periodic limit cycle with a large period appears. In order to reverse this degradation in dynamics of chaotic time-delay sampled system, the digital circuit has been supported by delaying buffers which utilize the jitter to break the periodic motion. Thus, the a periodic behavior of proposed full digital design resembles the original chaotic behavior. Designs of the system are tested on a field-programmable gate array (FPGA). Furthermore, two RNGs based on these designs are given and test results are presented in the paper. Tests indicate that when time-varying delay is included using propagation delay even 8-bit representation of the system shows the sensitive dependence on initial conditions.
Original language | English |
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Title of host publication | IEEE International Symposium on Circuits and Systems |
Subtitle of host publication | From Dreams to Innovation, ISCAS 2017 - Conference Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781467368520 |
DOIs | |
Publication status | Published - 25 Sept 2017 |
Event | 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: 28 May 2017 → 31 May 2017 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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ISSN (Print) | 0271-4310 |
Conference
Conference | 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 |
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Country/Territory | United States |
City | Baltimore |
Period | 28/05/17 → 31/05/17 |
Bibliographical note
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