FPGA Based Hardware Accelerator for Euler Equations with Finite Volume Method

Computational Fluid Dynamic (CFD) is of great importance in the design and analysis of aircraft. The utilization of CFD enables the improvement of aircraft design, cost reduction, enhanced energy efficiency, and optimization of aircraft performance. By conducting realistic CFD simulations prior to production, the performance of the designed aircraft can be thoroughly tested. CFD solves complex equations numerically to analyze fluid flow, hence requiring substantial computational power and time. Presently, high-core-count computers are available to facilitate these calculations. However, the cost of such computers is considerably high. Therefore, we propose the development of an Field Programmable Gate Array (FPGA) based CFD accelerator to reduce computation time and cost. The focus is on designing an FPGA based Euler Equations solver for high-speed flow simulations. The two-dimensional Euler Equations are derived and discretized using the Finite Volume Method (FVM). MATLAB scripts are developed for the solver, resulting in the generation of core script files that created intial model. A MATLAB simulator is developed using these files. The simulator’s performance is validated against ANSYS Fluent analysis. Once validated, the initial model are transferred to the MATLAB HDLcoder environment. In HDLcoder, hardware design is performed for a single finite volume, utilizing information from the simulation logger stored in the idea step. The model undergoes elaboration and high-level synthesis. The resulting HDLcoder model generates synthesizable HDL (Hardware Description Language) code for FPGA implementation. Verification and evaluation are conducted using the simulation logger results. FPGA resource utilization was analyzed and the speed of the accelerator was compared with the Central Process Unit (CPU).