Flexible hardware design for RSA and elliptic curve cryptosystems

Lejla Batina*, Geeke Bruin-Muurling, Siddika Berna Örs

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

23 Citations (Scopus)

Abstract

This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduced hardware accelerator features a design which can be varied from very small (less than 20 Kgates) targeting wireless applications, up to a very big design (more than 100 Kgates) used for network security. In latter option it can include a few dedicated large number arithmetic units each of which is a systolic array performing the Montgomery Modular Multiplication (MMM). The bound on the Montgomery parameter has been optimized to facilitate more secure ECC point operations. Furthermore, we present a new possibility for CRT scheme which is less vulnerable to side-channel attacks.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsTatsuaki Okamoto
PublisherSpringer Verlag
Pages250-263
Number of pages14
ISBN (Print)3540209964
DOIs
Publication statusPublished - 2004
Externally publishedYes

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2964
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Keywords

  • ECC
  • FPGA design
  • Hardware implementation
  • Montgomery multiplication
  • RSA
  • Side-channel attacks
  • Systolic array

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