First-Order Threshold Implementation of AES Against Side-Channel Attacks on FPGA

The Advanced Encryption Standard (AES) is widely used for secure data encryption in cryptographic systems. However, side-channel attacks, such as differential power analysis (DPA) and differential electromagnetic analysis (DEMA), exploit physical effects like power consumption and electromagnetic emissions to extract secret information from cryptographic systems. Masking methods, such as randomizing intermediate values in a cryptographic system, are commonly used as countermeasures against DPA and DEMA side-channel attacks. However, hardware glitches may make these countermeasures ineffective, leaving the system vulnerable to attacks. In this study, an AES system vulnerable to side-channel analysis was secured against such attacks using a first-order threshold implementation, which is also resilient to effects like glitches. The vulnerability of protected and unprotected systems to attacks was evaluated using Test Vector Leakage Assessment (TVLA). It was demonstrated that the absolute value of the t -value in TVLA for the protected system with threshold implementation is below the threshold of 4.5, indicating that the applied protection is resistant to firstorder side-channel attacks. After applying threshold implementation to an unprotected AES system, the LUT count increased by approximately 3.72 times, the flip-flop count by approximately 1.05 times, and the critical-path delay by approximately 2.28 times. The number of clock cycles required for the encryption process remained unchanged, as intended.