Fault tolerant register file design for MIPS AES-crypto microprocessor

Buse Ustaoglu; Berna Ors Yalcin

doi:10.1109/ICECS.2015.7440343

Fault tolerant register file design for MIPS AES-crypto microprocessor

Buse Ustaoglu, Berna Ors Yalcin

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.

Original language	English
Title of host publication	2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	442-445
Number of pages	4
ISBN (Electronic)	9781509002467
DOIs	https://doi.org/10.1109/ICECS.2015.7440343
Publication status	Published - 23 Mar 2016
Event	IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 - Cairo, Egypt Duration: 6 Dec 2015 → 9 Dec 2015

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	2016-March

Conference

Conference	IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Country/Territory	Egypt
City	Cairo
Period	6/12/15 → 9/12/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Access to Document

10.1109/ICECS.2015.7440343

Cite this

Ustaoglu, B., & Yalcin, B. O. (2016). Fault tolerant register file design for MIPS AES-crypto microprocessor. In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 (pp. 442-445). Article 7440343 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2016-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2015.7440343

@inproceedings{1868ed8dee0341d488e61c6a050d0390,

title = "Fault tolerant register file design for MIPS AES-crypto microprocessor",

abstract = "This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.",

author = "Buse Ustaoglu and Yalcin, {Berna Ors}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 ; Conference date: 06-12-2015 Through 09-12-2015",

year = "2016",

month = mar,

day = "23",

doi = "10.1109/ICECS.2015.7440343",

language = "English",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "442--445",

booktitle = "2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015",

address = "United States",

}

Ustaoglu, B & Yalcin, BO 2016, Fault tolerant register file design for MIPS AES-crypto microprocessor. in 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015., 7440343, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 2016-March, Institute of Electrical and Electronics Engineers Inc., pp. 442-445, IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, 6/12/15. https://doi.org/10.1109/ICECS.2015.7440343

Fault tolerant register file design for MIPS AES-crypto microprocessor. / Ustaoglu, Buse; Yalcin, Berna Ors.
2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 442-445 7440343 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2016-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fault tolerant register file design for MIPS AES-crypto microprocessor

AU - Ustaoglu, Buse

AU - Yalcin, Berna Ors

PY - 2016/3/23

Y1 - 2016/3/23

N2 - This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.

AB - This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.

UR - http://www.scopus.com/inward/record.url?scp=84964817271&partnerID=8YFLogxK

U2 - 10.1109/ICECS.2015.7440343

DO - 10.1109/ICECS.2015.7440343

M3 - Conference contribution

AN - SCOPUS:84964817271

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 442

EP - 445

BT - 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015

Y2 - 6 December 2015 through 9 December 2015

ER -

Ustaoglu B, Yalcin BO. Fault tolerant register file design for MIPS AES-crypto microprocessor. In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc. 2016. p. 442-445. 7440343. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2015.7440343

Fault tolerant register file design for MIPS AES-crypto microprocessor

Abstract

Publication series

Conference

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this