Abstract
In this study, various fault tolerant techniques have been handled for pipelined MIPS-32 microprocessor in order for correct operation in the presence of faults and reliability analysis have been performed. For this purpose, register file is focussed on due to the fact that it is one of the most important unit of microprocessor. Register files designed with the fault tolerant methods have been synthesized with Cadence RTL Compiler, area and maximum frequency results have been obtained based on TSMC-90 nm technology. Mathematical models have been presented with the assumption that transient faults occur with a Poisson distribution and bit failures are statistically independent for reliability analysis. The results and graphics have been given by using Octave.
Translated title of the contribution | Reliability analysis of MIPS-32 microprocessor register files designed with different fault tolerant techniques |
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Original language | Turkish |
Title of host publication | 2016 24th Signal Processing and Communication Application Conference, SIU 2016 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 2073-2076 |
Number of pages | 4 |
ISBN (Electronic) | 9781509016792 |
DOIs | |
Publication status | Published - 20 Jun 2016 |
Event | 24th Signal Processing and Communication Application Conference, SIU 2016 - Zonguldak, Turkey Duration: 16 May 2016 → 19 May 2016 |
Publication series
Name | 2016 24th Signal Processing and Communication Application Conference, SIU 2016 - Proceedings |
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Conference
Conference | 24th Signal Processing and Communication Application Conference, SIU 2016 |
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Country/Territory | Turkey |
City | Zonguldak |
Period | 16/05/16 → 19/05/16 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.