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Exploring Fault-Tolerance in RISC-V Architectures

  • Mustafa Ensar Iskin*
  • , Berna Ors Yalcin
  • , Ayse Yilmazer
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Fault tolerance is a critical aspect of modern electronic systems, particularly in environments like space, aviation, and automotive, where reliability is paramount. This paper examines the fault tolerance approaches in RISC-V architectures. Techniques such as spatial, temporal, and information redundancy are reviewed, with a focus on their integration into RISC-V-based systems. Comparative analysis of single-core and multi-core redundancy, including modular and heterogeneous approaches, demonstrates their impact on performance, energy efficiency, and cost. Testing methods ranging from simulation to real-world radiation exposure are evaluated. Finally, insights into future research opportunities are presented to guide the development of more robust and efficient fault-tolerant systems.

Original languageEnglish
Title of host publication2025 12th International Conference on Electrical and Electronics Engineering, ICEEE 2025
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages19-23
Number of pages5
ISBN (Electronic)9798331598440
DOIs
Publication statusPublished - 2025
Event12th International Conference on Electrical and Electronics Engineering, ICEEE 2025 - Istanbul, Turkey
Duration: 24 Sept 202526 Sept 2025

Publication series

Name2025 12th International Conference on Electrical and Electronics Engineering, ICEEE 2025

Conference

Conference12th International Conference on Electrical and Electronics Engineering, ICEEE 2025
Country/TerritoryTurkey
CityIstanbul
Period24/09/2526/09/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

  • DMR
  • ECC
  • Fault Tolerance
  • MBU
  • ODMR
  • Redundancy
  • SEU
  • TMR

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