Emulating CNN with template learning on FPGA

Erdem Kose; Mustak E. Yalcin

doi:10.1109/ECCTD.2017.8093280

Emulating CNN with template learning on FPGA

Erdem Kose, Mustak E. Yalcin

Department of Electronics and Communication Engineering

Gebze Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

A 2-D Cellular Neural Network structure with space invariant neural weights is widely used in image processing applications. Recent advances VLSI technology appears to be very promising to use discrete time CNNs for real time vision applications. In this paper, a system-on-chip implementation which consists of a new CNN emulator design and a processor which performs template learning algorithm is shown. SoC design is programmed to perform a sequential CNN operations on different input and state images with different templates. Furthermore, the presented SoC design allows that templates can be updated by a learning algoritm in run time. SoC design is realised on a target FPGA. Test results on FPGA and MATLAB are presented and compared with structural similarity map.

Original language	English
Title of host publication	2017 European Conference on Circuit Theory and Design, ECCTD 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538639740
DOIs	https://doi.org/10.1109/ECCTD.2017.8093280
Publication status	Published - 31 Oct 2017
Event	2017 European Conference on Circuit Theory and Design, ECCTD 2017 - Catania, Italy Duration: 4 Sept 2017 → 6 Sept 2017

Publication series

Name	2017 European Conference on Circuit Theory and Design, ECCTD 2017

Conference

Conference	2017 European Conference on Circuit Theory and Design, ECCTD 2017
Country/Territory	Italy
City	Catania
Period	4/09/17 → 6/09/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

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10.1109/ECCTD.2017.8093280

Cite this

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title = "Emulating CNN with template learning on FPGA",

abstract = "A 2-D Cellular Neural Network structure with space invariant neural weights is widely used in image processing applications. Recent advances VLSI technology appears to be very promising to use discrete time CNNs for real time vision applications. In this paper, a system-on-chip implementation which consists of a new CNN emulator design and a processor which performs template learning algorithm is shown. SoC design is programmed to perform a sequential CNN operations on different input and state images with different templates. Furthermore, the presented SoC design allows that templates can be updated by a learning algoritm in run time. SoC design is realised on a target FPGA. Test results on FPGA and MATLAB are presented and compared with structural similarity map.",

author = "Erdem Kose and Yalcin, {Mustak E.}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 European Conference on Circuit Theory and Design, ECCTD 2017 ; Conference date: 04-09-2017 Through 06-09-2017",

year = "2017",

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doi = "10.1109/ECCTD.2017.8093280",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Kose, E & Yalcin, ME 2017, Emulating CNN with template learning on FPGA. in 2017 European Conference on Circuit Theory and Design, ECCTD 2017., 8093280, 2017 European Conference on Circuit Theory and Design, ECCTD 2017, Institute of Electrical and Electronics Engineers Inc., 2017 European Conference on Circuit Theory and Design, ECCTD 2017, Catania, Italy, 4/09/17. https://doi.org/10.1109/ECCTD.2017.8093280

Emulating CNN with template learning on FPGA. / Kose, Erdem; Yalcin, Mustak E.
2017 European Conference on Circuit Theory and Design, ECCTD 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 8093280 (2017 European Conference on Circuit Theory and Design, ECCTD 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A 2-D Cellular Neural Network structure with space invariant neural weights is widely used in image processing applications. Recent advances VLSI technology appears to be very promising to use discrete time CNNs for real time vision applications. In this paper, a system-on-chip implementation which consists of a new CNN emulator design and a processor which performs template learning algorithm is shown. SoC design is programmed to perform a sequential CNN operations on different input and state images with different templates. Furthermore, the presented SoC design allows that templates can be updated by a learning algoritm in run time. SoC design is realised on a target FPGA. Test results on FPGA and MATLAB are presented and compared with structural similarity map.

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Emulating CNN with template learning on FPGA

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