Efficient Hardware Implementation of the Toom-Cook-4 Algorithm Using a Pipelined Architecture on FPGA

Multiplication is a critical operation in public-key cryptography, and efficient implementations are essential due to increasing key sizes in algorithms such as RSA and ECC. The Toom-Cook algorithm is a highly effective method for accelerating large-integer multiplication, particularly in applications requiring high-performance arithmetic such as cryptography. This paper presents an efficient hardware implementation of the Toom-Cook-4 multiplication algorithm targeting FPGA platforms. After individual implementation, all stages are integrated into a complete system. To achieve high throughput, a pipelined architecture is incorporated into the design. The system is implemented for 512-bit operands and is designed parametrically to support different input sizes. The overall system features a pipelined architecture capable of producing one output per clock cycle after an initial latency of 10 cycles, enabling highthroughput streaming operation. The final design utilizes 38,723 LUTs, 18,818 flip-flops, and 252 DSP blocks, with a critical path delay of 9.13 ns for 512-bit input operands.