Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks

Mohammadreza Esmali Nojehdeh; Sajjad Parvin; Mustafa Altun

doi:10.1109/ISVLSI51109.2021.00079

Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks

Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations. Also, to reduce hardware complexity, we implement convolutional layers under the time-multiplexed architecture where computing resources are re-used in the multiply-accumulate (MAC) blocks. A comprehensive evaluation of convolution layers shows using our proposed method when compared to the conventional MAC-based method results up to 97% and 50% reduction in dissipated power and computation time, respectively.

Original language	English
Title of host publication	Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Publisher	IEEE Computer Society
Pages	402-405
Number of pages	4
ISBN (Electronic)	9781665439466
DOIs	https://doi.org/10.1109/ISVLSI51109.2021.00079
Publication status	Published - Jul 2021
Event	20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 - Tampa, United States Duration: 7 Jul 2021 → 9 Jul 2021

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2021-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Country/Territory	United States
City	Tampa
Period	7/07/21 → 9/07/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Funding

ACKNOWLDGEMENT This work is supported by the TUBITAK-1001 projects #119E507 and Istanbul Technical University BAP projects #42446.

Funders	Funder number
TUBITAK-1001	119E507
Istanbul Teknik Üniversitesi	42446

Access to Document

10.1109/ISVLSI51109.2021.00079

Cite this

Nojehdeh, M. E., Parvin, S., & Altun, M. (2021). Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. In Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 (pp. 402-405). (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2021-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI51109.2021.00079

@inproceedings{e2893fb4b4334f0092fd768eb21e4f26,

title = "Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks",

abstract = "In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations. Also, to reduce hardware complexity, we implement convolutional layers under the time-multiplexed architecture where computing resources are re-used in the multiply-accumulate (MAC) blocks. A comprehensive evaluation of convolution layers shows using our proposed method when compared to the conventional MAC-based method results up to 97\% and 50\% reduction in dissipated power and computation time, respectively.",

author = "Nojehdeh, \{Mohammadreza Esmali\} and Sajjad Parvin and Mustafa Altun",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 ; Conference date: 07-07-2021 Through 09-07-2021",

year = "2021",

month = jul,

doi = "10.1109/ISVLSI51109.2021.00079",

language = "English",

series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

publisher = "IEEE Computer Society",

pages = "402--405",

booktitle = "Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021",

address = "United States",

}

Nojehdeh, ME, Parvin, S & Altun, M 2021, Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. in Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021. Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2021-July, IEEE Computer Society, pp. 402-405, 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, United States, 7/07/21. https://doi.org/10.1109/ISVLSI51109.2021.00079

Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. / Nojehdeh, Mohammadreza Esmali; Parvin, Sajjad; Altun, Mustafa.
Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021. IEEE Computer Society, 2021. p. 402-405 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2021-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks

AU - Nojehdeh, Mohammadreza Esmali

AU - Parvin, Sajjad

AU - Altun, Mustafa

PY - 2021/7

Y1 - 2021/7

N2 - In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations. Also, to reduce hardware complexity, we implement convolutional layers under the time-multiplexed architecture where computing resources are re-used in the multiply-accumulate (MAC) blocks. A comprehensive evaluation of convolution layers shows using our proposed method when compared to the conventional MAC-based method results up to 97% and 50% reduction in dissipated power and computation time, respectively.

AB - In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations. Also, to reduce hardware complexity, we implement convolutional layers under the time-multiplexed architecture where computing resources are re-used in the multiply-accumulate (MAC) blocks. A comprehensive evaluation of convolution layers shows using our proposed method when compared to the conventional MAC-based method results up to 97% and 50% reduction in dissipated power and computation time, respectively.

UR - https://www.scopus.com/pages/publications/85114961607

U2 - 10.1109/ISVLSI51109.2021.00079

DO - 10.1109/ISVLSI51109.2021.00079

M3 - Conference contribution

AN - SCOPUS:85114961607

T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

SP - 402

EP - 405

BT - Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021

PB - IEEE Computer Society

T2 - 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021

Y2 - 7 July 2021 through 9 July 2021

ER -

Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks

Abstract

Publication series

Conference

Bibliographical note

Funding

Access to Document

Other files and links

Fingerprint

Cite this