DVB-S alicisi için reed-solomon kod çözücü donanim gerçeklemesi

Translated title of the contribution: Reed-solomon decoder hardware implementation for DVB-S receiver

Seyyid M. Dilek, Berna Örs, Mesut Kartal

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

In this paper, a shortened Reed-Solomon decoder (n=204, k=188) is simulated using MATLAB and Maple programs within Digital Video Broadcasting - Satellite standards. Then, it is modelled and its hardware is implemented regarding to speedy, flexible, and straightforward production on FPGA using VHDL. Due to speed, flexibleness, and easy fabrication, the cellular-Array multiplication method is used for the commonly used arithmetic operation, finite field multiplication. Reformulated inverse-free Berlekamp-Messey Algorithm, capable of high speed and low complexity, is implemented succesfully for key equation solver unit.

Translated title of the contributionReed-solomon decoder hardware implementation for DVB-S receiver
Original languageTurkish
Title of host publication2013 21st Signal Processing and Communications Applications Conference, SIU 2013
DOIs
Publication statusPublished - 2013
Event2013 21st Signal Processing and Communications Applications Conference, SIU 2013 - Haspolat, Turkey
Duration: 24 Apr 201326 Apr 2013

Publication series

Name2013 21st Signal Processing and Communications Applications Conference, SIU 2013

Conference

Conference2013 21st Signal Processing and Communications Applications Conference, SIU 2013
Country/TerritoryTurkey
CityHaspolat
Period24/04/1326/04/13

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