Differential power analysis resistant hardware implementation of the RSA cryptosystem

Keklik Alptekin Bayam, Berna Ors

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Citations (Scopus)

Abstract

In this paper, RSA cryptosystem was implemented on an FPGA as resistant against Differential Power Analysis attacks. There are hardware and algorithmic countermeasures against power analysis attacks. This is the first FPGA realization of an algorithmic countermeasure which makes RSA resistant to power analysis attacks. Modular exponentiation is realized with Montgomery Modular Multiplication. The Montgomery modular multiplier has been realized with carry save adders. Carry save representation has been used throughout the RSA encryption algorithm. The protected implementation resulted in 66,66 MHz of clock frequency, 84,42 Kb/s of throughput, and 6,06 ms of total exponentiation time and occupied an area of 10986 slices with the use of the built-in block SelectRAM structure inside XCV1000E.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages3314-3317
Number of pages4
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: 18 May 200821 May 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Country/TerritoryUnited States
CitySeattle, WA
Period18/05/0821/05/08

Keywords

  • Carry save adder
  • Differential power analysis attack
  • Montgomery modular multiplier
  • Randomized table window method
  • RSA
  • Side-channel attacks

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