Design of new tiny circuits for aes encryption algorithm

K. Volkan Dalmisli; Berna Ors

doi:10.1109/ICSCS.2009.5414191

Design of new tiny circuits for aes encryption algorithm

K. Volkan Dalmisli, Berna Ors

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.

Original language	English
Title of host publication	3rd International Conference on Signals, Circuits and Systems, SCS 2009
DOIs	https://doi.org/10.1109/ICSCS.2009.5414191
Publication status	Published - 2009
Event	3rd International Conference on Signals, Circuits and Systems, SCS 2009 - Medenine, Tunisia Duration: 6 Nov 2009 → 8 Nov 2009

Publication series

Name	3rd International Conference on Signals, Circuits and Systems, SCS 2009

Conference

Conference	3rd International Conference on Signals, Circuits and Systems, SCS 2009
Country/Territory	Tunisia
City	Medenine
Period	6/11/09 → 8/11/09

Keywords

AES
ASIC
FPGA
Low area
Low power

Access to Document

10.1109/ICSCS.2009.5414191

Cite this

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title = "Design of new tiny circuits for aes encryption algorithm",

abstract = "Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.",

keywords = "AES, ASIC, FPGA, Low area, Low power",

author = "Dalmisli, {K. Volkan} and Berna Ors",

year = "2009",

doi = "10.1109/ICSCS.2009.5414191",

language = "English",

isbn = "9781424443987",

series = "3rd International Conference on Signals, Circuits and Systems, SCS 2009",

booktitle = "3rd International Conference on Signals, Circuits and Systems, SCS 2009",

note = "3rd International Conference on Signals, Circuits and Systems, SCS 2009 ; Conference date: 06-11-2009 Through 08-11-2009",

}

Dalmisli, KV & Ors, B 2009, Design of new tiny circuits for aes encryption algorithm. in 3rd International Conference on Signals, Circuits and Systems, SCS 2009., 5414191, 3rd International Conference on Signals, Circuits and Systems, SCS 2009, 3rd International Conference on Signals, Circuits and Systems, SCS 2009, Medenine, Tunisia, 6/11/09. https://doi.org/10.1109/ICSCS.2009.5414191

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AU - Dalmisli, K. Volkan

AU - Ors, Berna

PY - 2009

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N2 - Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.

AB - Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.

KW - AES

KW - ASIC

KW - FPGA

KW - Low area

KW - Low power

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U2 - 10.1109/ICSCS.2009.5414191

DO - 10.1109/ICSCS.2009.5414191

M3 - Conference contribution

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SN - 9781424443987

T3 - 3rd International Conference on Signals, Circuits and Systems, SCS 2009

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T2 - 3rd International Conference on Signals, Circuits and Systems, SCS 2009

Y2 - 6 November 2009 through 8 November 2009

ER -

Design of new tiny circuits for aes encryption algorithm

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Keywords

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