Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)

Sadik Iik; Fikret Basar Gencer; Mustafa Berke Yelten

doi:10.1109/SMACD.2018.8434894

Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)

Sadik Iik, Fikret Basar Gencer, Mustafa Berke Yelten

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a p-type channel TFT device with 6 terminals (4 gates, one drain and one source) has been proposed. The device has been constructed through Sentaurus TCAD suite. Simple logic gates (NOR, NAND, NOT and XOR) are built by using different input configurations applied to four gates of the device. Device simulations have revealed that all gates can operate at 5 V with full functionality. The performance of the logic gates has been shown to be good enough for simple applications in the large-area digital electronics systems.

Original language	English
Title of host publication	SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	77-80
Number of pages	4
ISBN (Print)	9781538651520
DOIs	https://doi.org/10.1109/SMACD.2018.8434894
Publication status	Published - 13 Aug 2018
Event	15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018 - Prague, Czech Republic Duration: 2 Jul 2018 → 5 Jul 2018

Publication series

Name	SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

Conference

Conference	15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018
Country/Territory	Czech Republic
City	Prague
Period	2/07/18 → 5/07/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

large-area electronics
logic gate
multiple gate transistors
TFT

Access to Document

10.1109/SMACD.2018.8434894

Cite this

Iik, S., Gencer, F. B., & Yelten, M. B. (2018). Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). In SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (pp. 77-80). Article 8434894 (SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMACD.2018.8434894

Iik, Sadik ; Gencer, Fikret Basar ; Yelten, Mustafa Berke. / Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 77-80 (SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).

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abstract = "In this paper, a p-type channel TFT device with 6 terminals (4 gates, one drain and one source) has been proposed. The device has been constructed through Sentaurus TCAD suite. Simple logic gates (NOR, NAND, NOT and XOR) are built by using different input configurations applied to four gates of the device. Device simulations have revealed that all gates can operate at 5 V with full functionality. The performance of the logic gates has been shown to be good enough for simple applications in the large-area digital electronics systems.",

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Iik, S, Gencer, FB & Yelten, MB 2018, Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). in SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design., 8434894, SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Institute of Electrical and Electronics Engineers Inc., pp. 77-80, 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018, Prague, Czech Republic, 2/07/18. https://doi.org/10.1109/SMACD.2018.8434894

Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). / Iik, Sadik; Gencer, Fikret Basar; Yelten, Mustafa Berke.
SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc., 2018. p. 77-80 8434894 (SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Iik S, Gencer FB, Yelten MB. Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). In SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc. 2018. p. 77-80. 8434894. (SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design). doi: 10.1109/SMACD.2018.8434894

Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)

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