Defect-tolerant logic synthesis for memristor crossbars with performance evaluation

Onur Tunali; M. Ceylan Morgul; Mustafa Altun

doi:10.1109/MM.2018.053631138

Defect-tolerant logic synthesis for memristor crossbars with performance evaluation

Onur Tunali, M. Ceylan Morgul, Mustafa Altun

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

In this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.

Original language	English
Article number	8474945
Pages (from-to)	22-31
Number of pages	10
Journal	IEEE Micro
Volume	38
Issue number	5
DOIs	https://doi.org/10.1109/MM.2018.053631138
Publication status	Published - 1 Sept 2018

Bibliographical note

Publisher Copyright:
© 1981-2012 IEEE.

Funding

This work is part of a project that has received funding from the European Union’s Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement No. 691178. This work is supported by the TUBITAK-Career project #113E760.

Funders	Funder number
Marie Skłodowska-Curie	113E760
Horizon 2020 Framework Programme	691178

Keywords

defect tolerance
hardware
logic synthesis
memristive crossbar
memristor

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10.1109/MM.2018.053631138

Cite this

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abstract = "In this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.",

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Defect-tolerant logic synthesis for memristor crossbars with performance evaluation

Abstract

Bibliographical note

Funding

Keywords

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