Defect-tolerant logic synthesis for memristor crossbars with performance evaluation

Onur Tunali, M. Ceylan Morgul, Mustafa Altun

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


In this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.

Original languageEnglish
Article number8474945
Pages (from-to)22-31
Number of pages10
JournalIEEE Micro
Issue number5
Publication statusPublished - 1 Sept 2018

Bibliographical note

Publisher Copyright:
© 1981-2012 IEEE.


This work is part of a project that has received funding from the European Union’s Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement No. 691178. This work is supported by the TUBITAK-Career project #113E760.

FundersFunder number
Marie Skłodowska-Curie113E760
Horizon 2020 Framework Programme691178


    • defect tolerance
    • hardware
    • logic synthesis
    • memristive crossbar
    • memristor


    Dive into the research topics of 'Defect-tolerant logic synthesis for memristor crossbars with performance evaluation'. Together they form a unique fingerprint.

    Cite this