CMOS high-performance UWB active inductor circuit

In order to maximize efficiency of the designed gyrator-based active inductor, advanced circuit techniques are used. Loss and noise are most important features of the AIs, where they should be low enough to have high-performance device. The gyrator-C topology is used to design a new low-loss and low-noise active inductor. The gyrator-C topology is potentially high-Q and all transistors are utilized in common-source configuration to have high impedance in input-output nodes. All transistors are free of body effect. The p-type differential pair input transistors and the feed forward path are employed to decrease noise of the proposed circuit. Additionally, inductance value and quality factor are adjusted by variation bias current which gives to the device tunable capability. HSPICE simulation results are presented to verify the performance of the circuit, where the 180 nm CMOS process and 1.8 V power supply are used. The noise voltage and power dissipation are less than 2.8 nV/ √ Hz and 1.3 mW, respectively.