CMOS design of a multi-input analog multiplier

Ali Naderi Saatlo, Serdar Ozoguz

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Citations (Scopus)

Abstract

This paper presents a new method in order to implement a high-performance CMOS multi-input analog multiplier circuit. The method is based on the effective realizations of exponential and logarithmic functions. The main advantage of this multiplier is the capability of having multiinput signals while keeping total harmonic distortion low. The circuit is designed and simulated using MATLAB software and HSPICE simulator using level 49 parameters (BSIM3v3) in 0.35μm standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 0.9%, a THD of 0.33% in 1MHz (20-A p-p), and a maximum power consumption of 0.89mW.

Original languageEnglish
Title of host publicationPRIME 2012; 8th Conference on Ph.D. Research in Microelectronics and Electronics
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages217-220
Number of pages4
ISBN (Electronic)9783800734429
Publication statusPublished - 2012
Event8th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2012 - Aachen, Germany
Duration: 12 Jun 201215 Jun 2012

Publication series

NamePRIME 2012; 8th Conference on Ph.D. Research in Microelectronics and Electronics

Conference

Conference8th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2012
Country/TerritoryGermany
CityAachen
Period12/06/1215/06/12

Keywords

  • Analog
  • CMOS
  • Component
  • Current mode
  • Multiinput
  • Multiplier circuit

Fingerprint

Dive into the research topics of 'CMOS design of a multi-input analog multiplier'. Together they form a unique fingerprint.

Cite this