Abstract
This paper aims to exploit approximate computing units in image processing systems and artificial neural networks. For this purpose, a general design methodology is introduced, and approximation-oriented architectures are developed for different applications. This paper proposes a method to compromise power/area efficiency of circuit-level design with accuracy supervision of system-level design. The proposed method selects approximate computational units that minimize the total computation cost, yet maintaining the ultimate performance. This is accomplished by formulating a linear programming problem, which can be solved by conventional linear programming solvers. Approximate computing units, such as multipliers, neurons, and convolution kernels, which are proposed by this paper, are suitable for power/area reduction through accuracy scaling. The formulation is demonstrated on applications in image processing, digital filters, and artificial neural networks. This way, the proposed technique and architectures are tested with different approximate computing units, as well as system-level requirement metrics, such as PSNR and classification performance.
Original language | English |
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Article number | 8585026 |
Pages (from-to) | 4726-4734 |
Number of pages | 9 |
Journal | IEEE Access |
Volume | 7 |
DOIs | |
Publication status | Published - 2019 |
Bibliographical note
Publisher Copyright:© 2013 IEEE.
Funding
This work was supported in part by TUBITAK under Grant 117E078 and in part by the European Union's Horizon 2020 Research and Innovation Program through the Marie Sklodowska-Curie Grant under Grant 691178. This work was supported in part by TUBITAK under Grant 117E078 and in part by the European Union’s Horizon 2020 Research and Innovation Program through the Marie Skłodowska-Curie Grant under Grant 691178.
Funders | Funder number |
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European Union's Horizon 2020 Research and Innovation Program | |
Marie Skłodowska-Curie | |
TUBITAK | 117E078 |
Horizon 2020 Framework Programme | 691178 |
Keywords
- Approximate computing
- artificial neural networks
- field programmable gate arrays
- high-level synthesis
- image processing