Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

Oguzhan Cik; Mustak Erhan Yalcin

doi:10.1109/SIU49456.2020.9302072

Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

Translated title of the contribution: A Hardware Accelerated Packet Classifier Design for A Network Router

Oguzhan Cik, Mustak Erhan Yalcin

Department of Electronics and Communication Engineering

Ulak Haberleşme A.Ş.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.

Translated title of the contribution	A Hardware Accelerated Packet Classifier Design for A Network Router
Original language	Turkish
Title of host publication	2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728172064
DOIs	https://doi.org/10.1109/SIU49456.2020.9302072
Publication status	Published - 5 Oct 2020
Event	28th Signal Processing and Communications Applications Conference, SIU 2020 - Gaziantep, Turkey Duration: 5 Oct 2020 → 7 Oct 2020

Publication series

Name	2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings

Conference

Conference	28th Signal Processing and Communications Applications Conference, SIU 2020
Country/Territory	Turkey
City	Gaziantep
Period	5/10/20 → 7/10/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Access to Document

10.1109/SIU49456.2020.9302072

Cite this

Cik, O., & Yalcin, M. E. (2020). Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. In 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings Article 9302072 (2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIU49456.2020.9302072

Cik, Oguzhan ; Yalcin, Mustak Erhan. / Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings).

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title = "Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi",

abstract = "In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.",

keywords = "AXI, CAM, FPGA, TCAM, fast lookup, hardware-software co-design, network, router",

author = "Oguzhan Cik and Yalcin, {Mustak Erhan}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 28th Signal Processing and Communications Applications Conference, SIU 2020 ; Conference date: 05-10-2020 Through 07-10-2020",

year = "2020",

month = oct,

day = "5",

doi = "10.1109/SIU49456.2020.9302072",

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series = "2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings",

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Cik, O & Yalcin, ME 2020, Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. in 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings., 9302072, 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 28th Signal Processing and Communications Applications Conference, SIU 2020, Gaziantep, Turkey, 5/10/20. https://doi.org/10.1109/SIU49456.2020.9302072

Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. / Cik, Oguzhan; Yalcin, Mustak Erhan.
2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9302072 (2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

AU - Cik, Oguzhan

AU - Yalcin, Mustak Erhan

PY - 2020/10/5

Y1 - 2020/10/5

N2 - In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.

AB - In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.

KW - AXI

KW - CAM

KW - FPGA

KW - TCAM

KW - fast lookup

KW - hardware-software co-design

KW - network

KW - router

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U2 - 10.1109/SIU49456.2020.9302072

DO - 10.1109/SIU49456.2020.9302072

M3 - Konferans katkısı

AN - SCOPUS:85100303729

T3 - 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings

BT - 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 28th Signal Processing and Communications Applications Conference, SIU 2020

Y2 - 5 October 2020 through 7 October 2020

ER -

Cik O, Yalcin ME. Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. In 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9302072. (2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings). doi: 10.1109/SIU49456.2020.9302072

Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

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