Abstract
Approximate computing is exploited in implementation of fully connected networks for classification problems. A multiplier structure whose area is scalable over accuracy through approximate computing is proposed. In order to employ the multipliers in a network, an area reduction algorithm is formed. It can adjust the approximation level of multipliers while still maintaining the target classification performance, without prior information on the value of network weights. Implementing on a Spartan6 FPGA, up to 79% area saving is recorded for various performance targets.
Original language | English |
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Title of host publication | SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 93-96 |
Number of pages | 4 |
ISBN (Print) | 9781538651520 |
DOIs | |
Publication status | Published - 13 Aug 2018 |
Event | 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018 - Prague, Czech Republic Duration: 2 Jul 2018 → 5 Jul 2018 |
Publication series
Name | SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design |
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Conference
Conference | 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018 |
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Country/Territory | Czech Republic |
City | Prague |
Period | 2/07/18 → 5/07/18 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.
Funding
ACKNOWLEDGEMENTS This project is funded by TUBITAK (The Scientific and Technological Research Council of Turkey), with the grant number 117E078.
Funders | Funder number |
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TUBITAK | |
Türkiye Bilimsel ve Teknolojik Araştirma Kurumu | 117E078 |
Keywords
- Approximate computing
- area reduction
- fully connected network