Application of surrogate modeling in variation-aware macromodel and circuit design

Ting Zhu*, Mustafa Berke Yelten, Michael B. Steer, Paul D. Franzon

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

This paper presents surrogate modeling as a solution to variation-aware macromodeling, circuit design, and device modeling. A scalable and high-fidelity IO buffer macromodel is created by integrating surrogate modeling with a physically-based model structure. Circuit performance surrogate models with design and variation parameters are efficient for design space exploration and performance yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. Surrogate-based optimization has great potential to speed up complex circuit design.

Original languageEnglish
Title of host publicationSIMULTECH 2011 - Proceedings of 1st International Conference on Simulation and Modeling Methodologies, Technologies and Applications
Pages502-508
Number of pages7
Publication statusPublished - 2011
Externally publishedYes
Event1st International Conference on Simulation and Modeling Methodologies, Technologies and Applications, SIMULTECH 2011 - Noordwijkerhout, Netherlands
Duration: 29 Jul 201131 Jul 2011

Publication series

NameSIMULTECH 2011 - Proceedings of 1st International Conference on Simulation and Modeling Methodologies, Technologies and Applications

Conference

Conference1st International Conference on Simulation and Modeling Methodologies, Technologies and Applications, SIMULTECH 2011
Country/TerritoryNetherlands
CityNoordwijkerhout
Period29/07/1131/07/11

Keywords

  • Circuit
  • Design exploration
  • Device model
  • Macromodel
  • Surrogate modeling
  • Variation-aware

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