Analyzing and comparing the Montgomery multiplication algorithms for their power consumption

Dilek Bayhan*, S. Berna Ors, Gokay Saldamli

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Citations (Scopus)

Abstract

This study analyses and compares the most popular Montgomery multiplication algorithms for their power dissipation on FPGA devices. Among various architectures proposed for Montgomery multiplication, we pick the parallel, sequential and systolic variants as the most revealing ones for our experimental needs. The synthesis results indicate that the sequential setting with a single cell gives the most efficient employment of the algorithm for dynamic power dissipation. However, if the energy is considered the parallel architecture is the most appropriate choice. Our analyses provides a fair comparison of power consumption of Montgomery multiplication algorithms on FPGAs giving hints to the engineers realizing the core of the most popular methods used in public-key cryptographic systems such as RSA, Diffie-Hellman, ECC and others.

Original languageEnglish
Title of host publicationProceedings, ICCES'2010 - 2010 International Conference on Computer Engineering and Systems
Pages257-261
Number of pages5
DOIs
Publication statusPublished - 2010
Event2010 6th International Conference on Computer Engineering and Systems, ICCES'2010 - Cairo, Egypt
Duration: 30 Nov 20101 Dec 2010

Publication series

NameProceedings, ICCES'2010 - 2010 International Conference on Computer Engineering and Systems

Conference

Conference2010 6th International Conference on Computer Engineering and Systems, ICCES'2010
Country/TerritoryEgypt
CityCairo
Period30/11/101/12/10

Keywords

  • Low power design
  • Montgomery multiplication
  • Parallel
  • Sequential
  • Systolic

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