Analyzing and comparing the AES architectures for their power consumption

It has been a decade since the block cipher Rijndael - with some minor changes - takes the name AES (Advanced Encryption Standard) and becomes the new block cipher standard of US government. Over the passed years, through deeper analysis and conducted measurements, AES has gained significant confidence for its security. Meanwhile, the sophistication in its realizations has also evolved considerably; system designers are now able to choose a suitable AES architecture tailored for their area and performance needs. Couple of years ago, the wider technological trend has shifted towards the power aware system design, hence, low power AES architectures gain importance over area and performance oriented designs. In this study, we examine and employ the low power design techniques in reducing the power consumption. These efforts allow us to come up with a slightly different architecture for s-box module. As a result, the power consumptions of AES over the Field Programmable Gate Arrays (FPGAs) are reduced. All described work and respective measurements are carried on Xilinx FPGA families and possible comparisons are made with the existing literature.