An FPGA implementation of an elliptic curve processor over GF(2 m)

Nele Mentens*, Siddika Berna Örs, Bart Preneel

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

29 Citations (Scopus)

Abstract

This paper describes a hardware implementation of an arithmetic processor which is efficient for elliptic curve (EC) cryptosystems, which are becoming increasingly popular as an alternative for public key cryptosystems based on factoring. The modular multiplication is implemented using a Montgomery modular multiplication in a systolic array architecture, which has the advantage that the clock frequency becomes independent of the bit length m.

Original languageEnglish
Title of host publicationProceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publicationVLSI in the Nanometer Era
Pages454-457
Number of pages4
Publication statusPublished - 2004
Externally publishedYes
EventProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
Duration: 26 Apr 200428 Apr 2004

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI

Conference

ConferenceProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
Country/TerritoryUnited States
CityBoston, MA
Period26/04/0428/04/04

Keywords

  • Elliptic Curve Cryptosystems
  • FPGA
  • Montgomery Modular Multiplication

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