An FPGA implementation of a RISC-V based SoC system for image processing applications

Erfan Gholizadehazari, Tuba Ayhan, Berna Ors

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Citations (Scopus)

Abstract

The Laplacian filter is one of the fundamental applications in image processing. In our work, the Laplacian filter has been applied to an image, and both hardware and software implementation of the filter has been studied. Our system consists of an OV7670 Camera module, Nexys 4 DDR FPGA board and VGA monitor to display the processed video stream. Mentioned process has forwarding tasks: camera module captures raw RGB data and writes to RAM, Laplacian filter IP processes raw image and the results written back to memory. VGA modules show output images to monitor. The Laplacian filter part considered in hardware and software implementation is compared in terms of time and area.

Original languageEnglish
Title of host publicationSIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665436496
DOIs
Publication statusPublished - 9 Jun 2021
Event29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021 - Virtual, Istanbul, Turkey
Duration: 9 Jun 202111 Jun 2021

Publication series

NameSIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings

Conference

Conference29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021
Country/TerritoryTurkey
CityVirtual, Istanbul
Period9/06/2111/06/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

  • Laplacian Filter
  • RISC-V
  • SoC

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