An Automated Setup for the Characterization of Time-Based Degradation Effects including the Process Variability in 40-nm CMOS Transistors

Xhesila Xhafa; Ali Dogus Gungordu; Didem Erol; Yavuzhan Yavuz; Mustafa Berke Yelten

doi:10.1109/TIM.2021.3090175

An Automated Setup for the Characterization of Time-Based Degradation Effects including the Process Variability in 40-nm CMOS Transistors

Xhesila Xhafa
, Ali Dogus Gungordu
, Didem Erol
, Yavuzhan Yavuz
, Mustafa Berke Yelten

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly.

Original language	English
Article number	9458293
Journal	IEEE Transactions on Instrumentation and Measurement
Volume	70
DOIs	https://doi.org/10.1109/TIM.2021.3090175
Publication status	Published - 2021

Bibliographical note

Publisher Copyright:
© 1963-2012 IEEE.

Funding

Manuscript received March 1, 2021; revised June 5, 2021; accepted June 8, 2021. Date of publication June 17, 2021; date of current version July 13, 2021. This work was supported by the Technological Research Council of Turkey under the project TÜB˙TAK 1001 118E253. The Associate Editor coordinating the review process was Zhengyu Peng. (Corresponding author: Mustafa Berke Yelten.) The authors are with the Department of Electronics and Communications Engineering, Istanbul Technical University, 34467 Istanbul, Turkey (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TIM.2021.3090175

Funders	Funder number
Technological Research Council of Turkey	TÜB˙TAK 1001 118E253

Keywords

Analog
bias temperature instability (BTI)
body effect
hot carrier injection (HCI)
integrated circuits
process variations
reliability
test chip
variability

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10.1109/TIM.2021.3090175

Cite this

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title = "An Automated Setup for the Characterization of Time-Based Degradation Effects including the Process Variability in 40-nm CMOS Transistors",

abstract = "This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly.",

keywords = "Analog, bias temperature instability (BTI), body effect, hot carrier injection (HCI), integrated circuits, process variations, reliability, test chip, variability",

author = "Xhesila Xhafa and Gungordu, \{Ali Dogus\} and Didem Erol and Yavuzhan Yavuz and Yelten, \{Mustafa Berke\}",

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doi = "10.1109/TIM.2021.3090175",

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AU - Erol, Didem

AU - Yavuz, Yavuzhan

AU - Yelten, Mustafa Berke

PY - 2021

Y1 - 2021

N2 - This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly.

AB - This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly.

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KW - body effect

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An Automated Setup for the Characterization of Time-Based Degradation Effects including the Process Variability in 40-nm CMOS Transistors

Abstract

Bibliographical note

Funding

Keywords

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