Abstract
The study presents a 10-bit differential SAR-Flash Hybrid ADC featuring an adaptive sampling mode. The design integrates the SAR and flash ADC architectures, using the lowpower advantages of SAR ADCs and the rapid performance of flash ADCs. Adaptive sampling enhances performance by dynamically adjusting the sample rate in response to the input signal characteristics, thereby improving resolution. The proposed ADC consumes 8.3 mW, and the simulated effective number of bits (ENOB) value increases from 8.84 to 9.16 bits while using the adaptive sampling mode.
| Original language | English |
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| Title of host publication | 2025 International Conference on Circuit, Systems and Communication, ICCSC 2025 |
| Editors | Mohammed El Ghzaoui, Bilal Aghoutane |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798331565282 |
| DOIs | |
| Publication status | Published - 2025 |
| Event | 2025 International Conference on Circuit, Systems and Communication, ICCSC 2025 - Fez, Morocco Duration: 19 Jun 2025 → 20 Jun 2025 |
Publication series
| Name | 2025 International Conference on Circuit, Systems and Communication, ICCSC 2025 |
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Conference
| Conference | 2025 International Conference on Circuit, Systems and Communication, ICCSC 2025 |
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| Country/Territory | Morocco |
| City | Fez |
| Period | 19/06/25 → 20/06/25 |
Bibliographical note
Publisher Copyright:© 2025 IEEE.
Keywords
- adaptive sampling
- Analog-to-digital converter (ADC)
- flash ADC
- successiveapproximation register (SAR)