TY - GEN
T1 - A practical authentication method of FPGA designs suitable for mass production
AU - Süzer, Orhun
AU - Kaya, Gürkan
AU - Dönmez, Faruk
AU - Saldamli, Gökay
AU - Yalçin, Müştak E.
PY - 2011
Y1 - 2011
N2 - Traditionally, IC companies were able to protect their IP assets by simply keeping these in safe. However, the new trends such as outsourcing and fabless IC development make the silicon processing and IC development more accessible. Therefore, IC authentication and IP (intellectual property) protection have become real world problems that industry eagerly seeks for efficient solutions. Most of the considerable proposals to these intense problems involve complicated cryptographic schemes and procedures that bring extra burden on system design. Moreover, if the target platform is a constraint environment, this burden is amplified and even the most efficient solutions become infeasible. Therefore, designers tend to use the ad-hoc methods that possibly have serious security risks. In this study, we seek practical solutions for the FPGAs (Field Programmable Gate Array) which represent a relatively small but important subset of hardware IP utilization.
AB - Traditionally, IC companies were able to protect their IP assets by simply keeping these in safe. However, the new trends such as outsourcing and fabless IC development make the silicon processing and IC development more accessible. Therefore, IC authentication and IP (intellectual property) protection have become real world problems that industry eagerly seeks for efficient solutions. Most of the considerable proposals to these intense problems involve complicated cryptographic schemes and procedures that bring extra burden on system design. Moreover, if the target platform is a constraint environment, this burden is amplified and even the most efficient solutions become infeasible. Therefore, designers tend to use the ad-hoc methods that possibly have serious security risks. In this study, we seek practical solutions for the FPGAs (Field Programmable Gate Array) which represent a relatively small but important subset of hardware IP utilization.
UR - http://www.scopus.com/inward/record.url?scp=84857311739&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84857311739
SN - 9786050102048
T3 - ELECO 2011 - 7th International Conference on Electrical and Electronics Engineering
SP - II293-II296
BT - ELECO 2011 - 7th International Conference on Electrical and Electronics Engineering
T2 - 7th International Conference on Electrical and Electronics Engineering, ELECO 2011
Y2 - 1 December 2011 through 4 December 2011
ER -