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A power-managed protocol processor for wireless sensor networks

  • M. Sheets*
  • , F. Burghardt
  • , T. Karalar
  • , J. Ammer
  • , Y. H. Chee
  • , J. Rabaey
  • *Corresponding author for this work
  • University of California at Berkeley

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

24 Citations (Scopus)

Abstract

Wireless sensor network applications, such as environmental control in smart building and ecological monitoring, require low-power nodes that operate their entire lifetime without changing batteries. This paper describes the power management architecture for a digital protocol processor for a sensor network node. Eight subsystems implement the baseband through application protocol layers and are controlled by a centralized power manager. The prototype chip, implemented in 130nm CMOS, operates at 1.0V with an average power consumption of 150μW during normal operation.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages212-213
Number of pages2
ISBN (Print)1424400066, 9781424400065
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event20th Annual Symposium on VLSI Circuits, VLSIC 2006 - Honolulu, HI, United States
Duration: 15 Jun 200617 Jun 2006

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
ISSN (Print)2158-5601
ISSN (Electronic)2158-5636

Conference

Conference20th Annual Symposium on VLSI Circuits, VLSIC 2006
Country/TerritoryUnited States
CityHonolulu, HI
Period15/06/0617/06/06

Keywords

  • Power management and MT-CMOS
  • Wireless sensor networks

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